1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a static Random-Access Memory device (SRAM) each memory cell of which has a function of a flip-flop including driver and transfer transistors formed by Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETS) and load elements formed by resistors or thin-film transistors (TFTS).
2. Description of the Prior Art
FIG. 1 shows a memory cell structure of a conventional SRAM of this sort, which is of the split word-line type.
As shown in FIG. 1, the layout of elements and their interconnections in the memory cell is symmetric with respect to a central point P of the cell, thereby improving the stability of the memory operation.
Two word lines WL101 and WL102 are arranged to extend along the X-ax is, which are laid out to be symmetric with respect to the central point P. Two bit lines (not shown) are arranged to extend along the Y-axis perpendicular to the X-axis, which are laid out to be symmetric with respect to the central point P.
Two active regions D101 and D102 are formed in a semiconductor substrate (not shown). The active regions D101 and D102 are laid out between the word lines WL101 and WL102 to be symmetric with respect to the central point P.
Two patterned conductive layers 101 and 102 are formed between the word lines WL101 and WL102 to extend along the Y-axis. The conductive layers 101 and 102 are laid out to be symmetric with respect to the central point P. The conductive layer 101 is overlapped with the active regions D101 and D102. The conductive layer 102 also is overlapped with the active regions D101 and D102.
The overlapped part 101a of the conductive layer 101 with the active region D101 serves as a gate electrode of a first driver MOSFET Td101. Parts D101a and D101b of the active region D101, which are located at each side of the part 101a, serve as a pair of source/drain regions of the first driver MOSFET Td101, respectively.
The overlapped part 102a of the conductive layer 102 with the active region D102 serves as a gate electrode of a second driver MOSFET Td102. Parts D102a and D102b of the active region D102, which are located at each side of the part 101a, serve as a pair of source/drain regions of the second driver MOSFET Td102, respectively.
The overlapped part WL101a of the word line WL101 with the active region D101 serves as a gate electrode of a first transfer MOSFET Ta101. The part D101b and a part D101c of the active region D101, which are located at each side of the part WL101a, serve as a pair of source/drain regions of the first transfer MOSFET Ta101, respectively.
The overlapped part WL102a of the word line WL102 with the active region D102 serves as a gate electrode of a second transfer MOSFET Ta102. The part D102b and a part D102c of the active region D102, which are located at each side of the part WL102a, serve as a pair of source/drain regions of the second transfer MOSFET Ta102, respectively.
A bit contact BC101 is laid out to be overlapped with the part D101c of the active region D101. A bit contact BC102 is laid out to be overlapped with the part D102c of the active region D102.
A ground contact GC101 is laid out to be overlapped with the part D101a of the active region D101. A ground contact GC102 is laid out to be overlapped with the part D102a of the active region D102.
Thus, the channels of the transfer MOSFETs Ta101 and Ta102 are formed under the overlapped part WL101a of the word line WL101 and the overlapped part WL102a of the word line WL102, respectively, both of which run along the Y-axis. On the other hand, the channels of the driver MOSFETs Td101 and Td102 are formed under the overlapped part 101a of the conductive layer 101 and the overlapped part 102a of the conductive layer 102, respectively, both of which run along the X-axis.
Accordingly, the channels of the transfer MOSFETs Ta101 and Ta102 are perpendicular to those of the driver MOSFETs Td101 and Td102.
FIG. 2 shows a memory cell structure of another conventional SRAM of this sort. This SRAM is of the split word-line type, and disclosed in the Japanese Non-Examined Patent Publication No. 6-169071 published in June 1994.
As shown in FIG. 2, similar to the conventional SRAM of FIG. 1, the layout of elements and their interconnections in the memory cell is symmetric with respect to a central point P of the cell, thereby increasing the channel length of the transfer MOSFETs.
Two word lines WL201 and WL202 are arranged to extend along the X-axis, which are laid out to be symmetric with respect to the central point P. The word lines WL201 and WL202 are bent outwardly.
Two bit lines (not shown) are arranged to extend along the Y-axis perpendicular to the X-axis, which are laid out to be symmetric with respect to the central point P.
Two active regions D201 and D202 are formed in a semiconductor substrate (not shown) to extend almost a straight line oblique to the Y-direction. The active regions D201 and D202 are laid out between the word lines WL201 and WL202 to be symmetric with respect to the central point P.
Two patterned conductive layers 201 and 202 are formed between the word lines WL201 and WL202 to extend along a straight line oblique to the Y-direction. The conductive layers 201 and 202 are laid out to be symmetric with respect to the central point P. The straight line along which the conductive layers 201 and 202 extends is inclined toward an opposite side to that of the active regions D201 and D202.
The conductive layer 201 is overlapped with the active regions D201 and D202. The conductive layer 202 also is overlapped with the active regions D201 and D202.
The overlapped part 201a of the conductive layer 201 with the active region D201 serves as a gate electrode of a first driver MOSFET Td201. Parts D201a and D201b of the active region D201, which are located at each side of the overlapped part 201a, serve as a pair of source/drain regions of the first driver MOSFET Td201, respectively.
The overlapped part 202a of the conductive layer 202 with the active region D202 serves as a gate electrode of a second driver MOSFET Td202. Parts D102a and D102b of the active region D202, which are located at each side of the overlapped part 201a, serve as a pair of source/drain regions of the second driver MOSFET Td202, respectively.
The overlapped part WL201a of the word line WL201 with the active region D201 serves as a gate electrode of a first transfer MOSFET Ta201. Parts D201c and D201d of the active region D201, which are located at each side of the overlapped part WL201a, serve as a pair of source/drain regions of the first transfer MOSFET Ta201, respectively.
The overlapped part WL202a of the word line WL202 with the active region D202 serves as a gate electrode of a second transfer MOSFET Ta202. Parts D202c and D202d of the active region D202, which are located at each side of the overlapped part WL202a, serve as a pair of source/drain regions of the second transfer MOSFET Ta202, respectively.
The overlapped parts WL201a and WL202a are located at their inclined parts, respectively.
A bit contact BC201 is laid out to be overlapped with the part D201d of the active region D201. A bit contact BC202 is laid out to be overlapped with the part D202d of the active region D202.
Thus, the channels of the transfer MOSFETs Ta201 and Ta202 are formed under the overlapped part WL201a of the word line WL201 and the overlapped part WL202a of the word line WL202, respectively, both of which run along the straight line oblique to the Y-axis. Similarly, the channels of the driver MOSFETs Td201 and Td202 are formed under the overlapped part 201a of the conductive layer 201 and the overlapped part 202a of the conductive layer 202, respectively, both of which run along the straight line oblique to the Y-axis.
Accordingly, the channels of the transfer MOSFETs Ta201 and Ta202 run in approximately the same direction as those of the driver MOSFETs Td201 and Td202.
However, in the memory cell of the conventional SRAM shown in FIG. 1, there is a problem that the parasitic capacitance between the bit lines and the wiring resistance are high and as a result, the high-speed operation of the SRAM is difficult to be realized. This problem is caused by the fact that the short side of the memory cell becomes shorter and the long side thereof becomes longer (in other words, the aspect ration of the memory cell becomes large), thereby decreasing the pitch of the bit lines and increasing the wiring or interconnection length.
In the memory cell of the conventional SRAM shown in FIG. 2, the above problem of the decreased pitch of the bit lines and the increased wiring/interconnection length is solved to some extent. However, there is a problem that the performance of the memory cell tends to fluctuate, which is caused by the following reason. As described previously, the overlapped parts WL201a and WL202a of the word lines WL201a and WL202a are located at their inclined parts, respectively. Therefore, if some overlay or placement error of the word lines WL201 and WL202 occurs with respect to the corresponding active regions D201 and D202 during a lithography process, the performance of the transfer MOSFETs Ta201 and 202 will fluctuate to a large extent.
Also, the parts D201d and D202d of the active regions D201 and D202 are located outside the corresponding word lines WL201 and WL202, and are angled at a specific value, respectively. The bit contacts BC201 and BC202 are laid out to be overlapped with the parts D201d and D202d, respectively. As a result, if some overlay or placement error of the bit contacts BC201 and BC202 occurs with respect to the corresponding active regions D201 and D202 during a lithography process, the contact resistance of the bit contacts BC201 and BC202 tends to be unbalanced over an allowable extent.